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i table of contents 1. general description ......................................................................................................... ..............1 2. features .................................................................................................................... ...........................1 3. ordering information........................................................................................................ .............1 5. functional block descriptions .............................................................................................. ..3 lcd polarity reverse signal generator.......................................................................................... .....3 clock signal generator ......................................................................................................... ................3 -v1 discharge circuit .......................................................................................................... ...................3 column driver voltage generator ................................................................................................ ........3 row driver voltage generator ................................................................................................... ...........3 row driver voltage conversion circuit .......................................................................................... .....3 vdd_row voltage generator...................................................................................................... .........3 +v1 voltage generator.......................................................................................................... .................3 6. pins assignment ............................................................................................................. ....................4 7. pin description ............................................................................................................. ......................5 8. dc characteristics .......................................................................................................... ................8 maximum ratings................................................................................................................ ...................8 9. electrical characteristics .................................................................................................. ................9 10. ac characteristics ......................................................................................................... .............10 input timing characteristics................................................................................................... ............10 output timing characteristics.................................................................................................. ..........11 11. explanation of functions................................................................................................... ......12 lcd polarity reverse signal generator.......................................................................................... ...13 clock signal generator ......................................................................................................... ..............14 driver voltage generator....................................................................................................... ..............14
ii contrast control circuit ....................................................................................................... ...............15 +v1 voltage generator.......................................................................................................... ...............15 -v1 and +v1 discharge circuit .................................................................................................. ..........16 power up and power down sequence............................................................................................... 16 12. application circuit (SSD1730 5x step-up mode).................................................................17 13. package dimensions......................................................................................................... ............18
solomon systech limited solomon systech limited solomon systech limited solomon systech limited semiconductor technical data this document contains information on a new product. specifications and information herein are subject to change without notic e. ic manufactured under motif license including u.s. patent no. 5,420,604 copyright ? 2001 solomon systech limited rev 2.0 04/2002 SSD1730 advanced infomation SSD1730 mla power chip cmos 1. general description the SSD1730 is a power chip for operating four-line mla (multi line addressing) lcd drivers. it consists of a cmos charge pump-type voltage converter that can generate all the bias voltages required for the four-line mla drive based on a single power supply input. this can be used for the system that is formed by a column (segment) driver such as ssd1870 and a row (common) driver such as ssd1881. such type of display system is able to produce a module with lower power consumption when comparing with the conventional driving method. 2. features single power supply operation, +2.4v to +3.6v low current consumption two step-up modes, 5x or 6x step-up by internal charge pump dc/dc converter internal lcd voltage generator to generate all lcd voltages required for 4-line mla driving external contrast control internal ?v1 discharge circuit to discharge the residual charge at the row driver negative voltage-side power supply voltage terminal ?v1 internal ?power off? function using an external signal equipped internally with a lcd polarity reverse signal generator polarity reversed period in the range of 2p to 17p available in 48 pin qfp package (0.5 mm terminal pitch) 3. ordering information ordering part number package dimension package form SSD1730ql3 7 mm x 7mm 48 lqfp table 1 - ordering information
solomon rev 2.0 04/2002 SSD1730 2 4. block diagram column (segment) driver voltage gener- ator row (common) driver voltage generator lcd polarity reverse signal generator clock signal generator -v1 discharge circuit c1p c1n c2p c2n -v3 c3p c3n v2 c4p c4n c1pb c1nb -v3b hc c5p c5n vem c6n vee c8n vdd_row -v1 ab xbb l0 l1 l2 l3 fr xfr lp xslp vdd_pwr vss row driver voltage conversion circuit vdd_row voltage generator +v1 voltage generator -v2 c7n figure 1 - block diagram
SSD1730 rev 2.0 04/2002 solomon 3 5. functional block descriptions lcd polarity reverse signal generator this circuit generates the polarity reverse signals fr and xfr from the pulse signal lp. the polarity reversal interval is controlled by four pins l0, l1, l2 & l3 and the range is from 2p to 17p (1p is equal to one lp period), table 15 shows their relationship. the polarity of the fr signal and the xfr signal are mutually opposite, so that the upper and lower screens can be driven mutually in opposite phases when a two-screen drive panel is used. clock signal generator this circuit generates the clock for the charge pump from the pulse signal lp. when the display control signal xslp is set to vss, the clock will stop and the voltage converter will halt. for normal display mode, xslp must be tied to vdd_pwr. besides, this circuit also generates the signals ab & xbb which are the clocks for the column driver voltage generator and the row driver voltage generator. figure 7 shows their timing characteristics. -v1 discharge circuit when the display is off or the power is off, this circuit will discharge the residual charges at the negative voltage level-sid e power supply voltage terminal ?v1 of the row driver. column driver voltage generator this circuit accompanying with external components generates voltages for column driver. in SSD1730, three voltage outputs including v2, -v2 and -v3 will be generated and their voltage levels are based on the supply voltage vdd_pwr. their relationship is v2 = vdd_pwr/2, -v2 = -(vdd_pwr/2) and ?v3 = -vdd_pwr. row driver voltage generator this voltage generator consists of three circuits (1) row driver voltage conversion circuit, (2) vdd_row voltage generator and (3) +v1 voltage generator. row driver voltage conversion circuit this circuit generates vee voltage which is used to generate +v1 & -v1 power supply voltages for row driver. there are two step-up modes 5x and 6x which are set by the hc pin. when hc pin is tied to vss, 5x step-up mode is chosen. when hc pin is tied to -v3b, 6x step-up mode is chosen. in SSD1730, vdd_pwr is taken as the reference, vee is equal to -4 x vdd_pwr at 5x step-up mode while vee is equal to -5 x vdd_pwr at 6x step-up mode. for the contrast adjustment, it is performed through the use of an external emitter follower circuit to adjust vee to generate ?v1, this contrast control circuit is shown in figure 9. vdd_row voltage generator vdd_row voltage generator is used to generate vdd_row, which is the power supply to the logic circuit of a row driver. +v1 voltage generator +v1 voltage generator accompanies with an external mos transistor to generate +v1 voltage, which is required for the row driver. figure 10 shows the accompanying external circuit for generating +v1 voltage.
solomon rev 2.0 04/2002 SSD1730 4 6. pins assignment the package of SSD1730 is 48 lqfp and table 2 shows its pin assignment. figure 2 - pinout diagram pin# signal name pin# signal name pin# signal name pin# signal name 1 -v1 13 -v3b 25 nc2 37 l0 2 c8n 14 c1nb 26 nc 3 38 l1 3 vdd_row 15 vss 27 -v3 39 l2 4 c7n 16 c1pb 28 c2p 40 l3 5 vss 17 vdd_pwr 29 vdd_pwr 41 vss 6 vee 18 c4n 30 c1p 42 lp 7 c6n 19 -v2 31 vss 43 fr 8 vem 20 c4p 32 c3n 44 xfr 9 c5n 21 -v3 33 v2 45 xslp 10 hc 22 vss 34 nc4 46 xtst 11 nc1 23 c1n 35 c3p 47 ab 12 c5p 24 c2n 36 vdd_pwr 48 xbb table 2 - pin assignment table pin 1
SSD1730 rev 2.0 04/2002 solomon 5 7. pin description key: i =input o =output i/o = bi-directional (input/output) p = power pin nc = dummy pin pin name type pin# description vdd_pwr p 17, 29 &36 power supply pin vss p 5, 15, 22, 31 & 41 ground pin table 3 - power supply pins pin name type pin# description l0 to l3 i 37 to 40 these input pins are used to set the polarity reversal interval ranging from 2p to 17p. fr o 43 this is an output pin and the fr signal is generated from the lcd polarity reverse signal generator. xfr o 44 this is an output pin and the xfr signal is also generated from the lcd polarity reverse signal generator. this signal is a reverse phase from fr signal. table 4 - pins for frame signal generator pin name type pin# description lp i 42 this input pin is used to generate the charge pump clock and the polarity reverse signal fr and xfr. a pulse signal with a period of 1p should be fed into this pin. xslp i 45 this input pin is used to switch on or off the display. when it is set to vss level, the clock and the operations of the voltage converter will be stop. the display will be off. when it is set to vdd_pwr level, the display will be on. table 5 - pins for clock signal generator
solomon rev 2.0 04/2002 SSD1730 6 pin name type pin# description -v1 i/o 1 this is the row driver negative voltage level power supply voltage terminal. the ?v1 is an input signal to the contrast adjustment circuit this is used to adjust the display contrast. besides, this is the power supply to the +v1 voltage generator control circuit. table 6 - pins for ?v1 discharge circuit pin name type pin# description c1p i/o 30 the positive-side connection terminal for a capacitor c1 to generate -v3 output voltage. (refer to the application circuit) c1n i/o 23 the negative-side connection terminal for a capacitor c1 to generate -v3 output voltage. (refer to the application circuit) c2p i/o 28 the positive-side connection terminal for a capacitor c2 to generate -v3 output voltage. (refer to the application circuit) c2n i/o 24 the negative-side connection terminal for a capacitor c2 to generate -v3 output voltage. (refer to the application circuit) -v3 o 21, 27 this is -v3 output voltage, which is for the power supply of segment driver. c3p i/o 35 the positive-side connection terminal for a capacitor c3 to generate v2 output voltage. (refer to the application circuit) c3n i/o 32 the negative-side connection terminal for a capacitor c3 to generate v2 output voltage. (refer to the application circuit) v2 i/o 33 this is v2 output voltage which is for the power supply of segment driver. c4p i/o 20 the positive-side connection terminal for a capacitor c4 to generate -v2 output voltage. (refer to the application circuit) c4n i/o 18 the negative-side connection terminal for a capacitor c4 to generate -v2 output voltage. (refer to the application circuit) -v2 o 19 this is -v2 output voltage which is for the power supply of segment driver. table 7 - pins for column (segment) driver voltage generator
SSD1730 rev 2.0 04/2002 solomon 7 pin name type pin# description pins for vdd_row voltage generator c8n i/o 2 the negative-side connection terminal for a capacitor c11 to generate vdd_row output voltage. (refer to the application circuit) vdd_row o 3 this is vdd_row output voltage which is the power supply to the logic circuit part of row driver. pins for +v1 voltage generator ab o 47 this is the clock output for the external n-channel mos transistor control in the +v1 voltage generator circuit. xbb o 48 this is the clock output for the external p-channel mos transistor control in the +v1 voltage generator circuit. c7n i/o 4 the negative-side connection terminal for a capacitor c18 to generate +v1 output voltage. (refer to the application circuit) pins for row driver voltage conversion circuit c1pb i/o 16 the positive-side connection terminal for a capacitor c10 and c11 to generate -v3b output voltage. (refer to the application circuit) c1nb i/o 14 the negative-side connection terminal for a capacitor c10 to generate -v3b output voltage. (refer to the application circuit) -v3b o 13 this is -v3b output voltage equipped as the middle voltage level for generating vee output voltage. hc i 10 this pin is used to select 5x or 6x step-up mode. when it is tied to vss, 5x step-up mode will be set. when it is tied to -v3b, 6x step-up mode will be set. c5p i/o 12 the positive-side connection terminal for a capacitor c8 and c9 to generate vem output voltage. (refer to the application circuit) c5n i/o 9 the negative-side connection terminal for a capacitor c8 to generate vem output voltage. (refer to the application circuit) vem o 8 this is vem output voltage equipped as the middle voltage level for generating vee output voltage. c6n i/o 7 the negative-side connection terminal for a capacitor c9 to generate vee output voltage. (refer to the application circuit) vee o 6 this is vee output voltage. table 8 - pins for row (common) driver voltage generator pin name type pin# description xtst i 46 this is a test pin. this pin must be tied to the vdd_pwr level in normal application. nc,1 nc2, nc3, nc4 nc 11, 25, 26, 34 dummy pins. these pins must be left open & unconnected in normal application. table 9 - test circuit pins and dummy pins
solomon rev 2.0 04/2002 SSD1730 8 8. dc characteristics maximum ratings symbol parameter value unit vdd_pwr supply voltage 3.7 v -v1 row driver negative supply voltage vee?0.3 to 0.3 v v in input voltage -0.3 to vdd_pwr+3.0 v i dd input current 10 ma i v2 output current at v2 6 ma i -v2 output current at -v2 6 ma i -v3 output current at -v3 5 ma i vee output current at vee 1 ma i vdd_row output current at vdd_row 0.1 ma t a operating temperature -20 to +85 c t stg storage temperature range -65 to +150 c table 10 - maximum ratings for dc characteristics (voltage referenced to vss, t a =25c) maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the limits shown in the electrical characteristics table. this device contain circuitry to protect the inputs against damage due to high static voltages of electric fields; however, it is advised that normal precautions to be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. all dummy pins and nc pins must be left open & unconnected. do not connect or group dummy pins or nc pins together.
SSD1730 rev 2.0 04/2002 solomon 9 9. electrical characteristics symbol parameter test condition min typ max unit vdd_pwr supply voltage range (absolute value referenced to vss) 2.4 3.3 3.6 v -v1 row driver negative supply voltage range (absolute value referenced to vss) vee+0.6 -- -v3 v istd standby mode supply current drain at vdd_pwr vdd_pwr=2.4v to 3.6v, display off (xslp=vil). -- 2 5 a i dp1 display mode supply current drain at vdd_pwr in 5x step-up mode vdd_pwr=2.7v, 5x step-up, lp period=69 s, lp width=1 s, display on (xslp=v ih ), no loading -- 270 380 a i dp2 display mode supply current drain at vdd_pwr in 6x step-up mode vdd_pwr=2.7v, 6x step-up, lp period=69 s, lp width=1 s, display on (xslp=v ih ), no loading -- 350 480 a vdd_pwr =2.7v -- -12.25 -- v vee output voltage at vee pin 6x step-up, lp period=69 s, lp width=1 s, display on (xslp=v ih ), io=0.4ma (from vss) vdd_pwr =2.4v -- -10.85 -- v vdd_pwr =2.7v -- -v1+2.7 -- v vdd_row output voltage at vdd_row pin 6x step-up, lp period=69 s, lp width=1 s, display on (xslp=v ih ), io=0.02ma (to ? v1) vdd_pwr =2.4v -- -v1+2.4 -- v vdd_pwr =2.7v -- 1.313 -- v v2 output voltage at v2 pin 6x step-up, lp period=69 s, lp width=1 s, display on (xslp=v ih ), io=2ma (to vss) vdd_pwr =2.4v -- 1.16 -- v vdd_pwr =2.7v -- -1.276 -- v -v2 output voltage at -v2 pin 6x step-up, lp period=69 s, lp width=1 s, display on (xslp=v ih ), io=2ma (from vss) vdd_pwr =2.4v -- -1.134 -- v vdd_pwr =2.7v -- -2.646 -- v -v3 output voltage at -v3 pin 6x step-up, lp period=69 s, lp width=1 s, display on (xslp=v ih ), io=1ma (from vss) vdd_pwr =2.4v -- -2.352 -- v v ih v il input high voltage at pins: lp, xslp, l0, l1, l2, l3 and xtst input low voltage at pins : lp, xslp, l0, l1, l2, l3 and xtst vdd_pwr = 2.4v - 3.6v 0.8*vdd_pwr 0 -- -- vdd_pwr 0.2*vdd_pwr v v oh v ol output high voltage at pins : xbb, ab, fr and xfr output low voltage at pins : xbb, ab, fr and xfr vdd_pwr = 2.4v - 3.6v, iout=-20 a vdd_pwr = 2.4v - 3.6v, iout=-20 a vdd_pwr-0.1 0 -- -- vdd_pwr 0.1 v table 11 - electrical characteristics (voltage referenced to vss, ta=25c)
solomon rev 2.0 04/2002 SSD1730 10 10. ac characteristics input timing characteristics symbol parameter min typ max unit t lpc lp period 50 70 125 s t lpw lp width 70 1000 *2000 ns t lpr lp rise time -- -- 10 ns t lpf lp fall time -- -- 10 ns table 12 - input timing characteristics (voltage referenced to vss, vdd_pwr = 2.4 to 3.6v, t a = 25 c) remark *: it is noted that the wider the positive lp pulse with, the higher the output impedance of the output voltage. the chip can function with positive lp pulse width in excess of 2000ns, but high output impedance will be found. t lpw t lpc t lp r t lpf lp figure 3 - timing characteristics for input pin lp
SSD1730 rev 2.0 04/2002 solomon 11 output timing characteristics lp pulse width = 1000ns, -v1 = vee + 0.6v, 6x step-up mode application symbol parameter min typ max unit t frr fr/xfr signal rise delay time (with loading = 50pf) 330 -- 3300 ns t frf fr/xfr signal fall delay time (with loading = 50pf) 330 -- 3300 ns t abr ab signal rise delay time 230 -- 2000 ns t abf ab signal fall delay time 180 -- 1900 ns t xbbr xbb signal rise delay time 130 -- 1100 ns t xbbf xbb signal fall delay time 280 -- 3200 ns t offr rising edge output phase differential time 1000 -- 2400 ns t offf falling edge output phase differential time 1000 -- 2200 ns t c7nr c7n signal rising edge delay time 270 -- 2400 ns t c7nf c7n signal falling edge delay time 490 -- 3800 ns table 13 - output timing characteristics lp fr xfr ab xbb t frr t frf t abr t xbb r t offr t c7 nf t abf t xbbf t offf t c7nr t c7nr c7n vss vl vl vss v ss- 1. 0v vl+1 .0v t c7nf figure 4 - output timing characteristics -v1 -v1 -v1+1.0 v
solomon rev 2.0 04/2002 SSD1730 12 11. explanation of functions this SSD1730 is a power chip for operating four-line mla lcd drivers. it consists of a cmos charge pump-type voltage generator which can produce all of the bias voltages for a four-line mla driven. SSD1730 power chip can be used as a voltage generator to a display system formed by column driver such as ssd1870 and row driver such as ssd1881. in SSD1730, all output voltages are generated or reference from supply power vdd_pwr. the volt- age levels at 5x or 6x step-up mode can be calculated by the logical formulas that are summarized in table 14. figure 5 - voltage levels relationship between power chip, column driver and row driver 5x step-up mode 6x step-up mode logical formula voltage level (vdd_pwr=3.3v) logical formula voltage level (vdd_pwr=3.3v) +v1=-(-v1) =4 x (vdd_pwr-vss) - 13.2 - +v1=-(-v1) =5 x (vdd_pwr-vss) - 16.5 - v3=vdd_pwr-vss 3.3 v3=vdd_pwr-vss 3.3 v2=0.5 x (vdd_pwr-vss) 1.65 v2=0.5 x (vdd_pwr-vss) 1.65 vc=vss 0.0 vc=vss 0.0 -v2=-0.5 x (vdd_pwr-vss) -1.65 -v2=-0.5 x (vdd_pwr-vss) -1.65 -v3=-v3b=-(vdd_pwr-vss) -3.3 -v3=-v3b=-(vdd_pwr-vss) -3.3 vem=-2 x (vdd_pwr-vss) -6.6 vem=-3 x (vdd_pwr-vss) -9.9 vdd_row=-3 x (vdd_pwr- vss) + -9.9 + vdd_row=-4 x (vdd_pwr- vss) + -13.2 + -v1=-4 x (vdd_pwr-vss) + -13.2 + -v1=-5 x (vdd_pwr-vss) + -16.5 + vee=-4 x (vdd_pwr-vss) -13.2 vee=-5 x (vdd_pwr-vss) -16.5 table 14 - logical formula for SSD1730 (vss = 0.0v) where is a variable and it must greater than or equal to 0 ( 0) . in practice, it represents contrast adjustment value. SSD1730 power chip ssd1881 row driver ssd1870 column driver external components vdd_pwr vss v dd_pw r v 2 v ss - v 2 - v 3 v dd_row - v 1 v ee v 3 v2 vss -v2 -v3 +v1 +v1 vc vdd_row -v1
SSD1730 rev 2.0 04/2002 solomon 13 lcd polarity reverse signal generator this circuit generates the polarity reverse signals fr and xfr from the 1p period pulse signal lp. the polarity reversal period ranging from 2p to 17p is controlled by four pins l0, l1, l2 & l3. in such case, the upper and lower screens can be driven in mutually opposite phases when a two-screen drive panel is used, the polarity of the fr signal and the xfr signal are mutually opposite. the timing of the output transitions is synchronized with the falling edge of the lp signal. figure 6 shows the timing diagram of lp, fr and xfr signals. table 15 shows the relationship between the number of lp (numlp) during the frame interval and the settings of l0 to l3. xslp fr xfr lp 1p pe riod numlp num lp figure 6 - timing characteristics of lp, fr and xfr l0 l1 l2 l3 time number of lp (numlp) 0 0 0 0 17p lp signal 17 th pulse 1 0 0 0 2p lp signal 2 nd pulse 0 1 0 0 3p lp signal 3 rd pulse 1 1 0 0 4p lp signal 4 th pulse 0 0 1 0 5p lp signal 5 th pulse 1 0 1 0 6p lp signal 6 th pulse 0 1 1 0 7p lp signal 7 th pulse 1 1 1 0 8p lp signal 8 th pulse 0 0 0 1 9p lp signal 9 th pulse 1 0 0 1 10p lp signal 10 th pulse 0 1 0 1 11p lp signal 11 th pulse 1 1 0 1 12p lp signal 12 th pulse 0 0 1 1 13p lp signal 13 th pulse 1 0 1 1 14p lp signal 14 th pulse 0 1 1 1 15p lp signal 15 th pulse 1 1 1 1 16p lp signal 16 th pulse table 15 - relationship between nlp an l0 to l3
solomon rev 2.0 04/2002 SSD1730 14 clock signal generator this circuit generates the clock for charge pump circuit from the pulse signal lp. when the display off control signal xslp is set to vss, the clock will stop and the voltage converter will halt. the signal clocks ab and xbb for the column driver voltage generator and the row driver voltage generator are also generated by this circuit. input signal xslp input signal lp output signal ab out p ut si g nal xbb figure 7 - timing diagram for lp, ab and xbb driver voltage generator this circuit generates all voltage levels which are required to drive both the row driver and the column driver. the voltage converter circuit comprises a cmos charge pump-type dc/dc converter which is formed by five individual voltage generator circuits including 1) column driver voltage generator, 2) row driver voltage conversion circuit, 3) vdd_row voltage generator circuit, 4) +v1 voltage generator circuit and 5) external contrast control circuit. figure 8 shows the relationship between these voltage generator circuits and table 14 summarized all logical formulas which can be used to calculated these voltage levels. besides, in order to generate these voltages, external capacitors for the charge pump are necessary. application circuit shows their connections figure 8 - voltage generator control circuit v 3 v2 vc -v2 -v3 vdd_row +v1 vee -v1 column driver voltage generator v dd_row voltage generator circuit +v1 voltage generator circuit ext. contrast control circuit row driver voltage conversion circuit row driver voltage generator - v 3b vem v dd_pw r vss
SSD1730 rev 2.0 04/2002 solomon 15 contrast control circuit the display contrast level ?v1 is controlled by an external contrast adjustment circuit. figure 9 shows the typical connection of contrast control circuit. -v3b vl vee SSD1730a vl 2sa 500k 510k figure 9 - typical connection of contrast control circuit +v1 voltage generator this circuit generates voltage level +v1 which is the positive power supply to row driver. signal ab and xbb are the clock for this generator circuit. figure 10 shows the typical connection of the +v1 voltage generator. xbb c7n ab SSD1730a vh 1.0uf 3.3m 2sj 470pf 1.0pf 2sj figure 10 - typical connection of +v1 voltage generator - v 1 - v 1 +v1
solomon rev 2.0 04/2002 SSD1730 16 -v1 and +v1 discharge circuit when xslp is set to vss level, the internal ?v1 discharge circuit will be triggered and the residual charge at the row driver negative voltage-side power supply voltage terminal ?v1 will be discharged to the vss level. however, the residual charge at the row driver positive voltage-side power supply terminal +v1 can be discharged to the vss level through an external mos transistor. figure 11 shows the typical connection of the +v1 discharge circuit. xslp vss SSD1730a 3.3m 2sk 2sk vh figure 11 - typical connection of +v1 discharge circuit power up and power down sequence proper power up sequence and power down sequence are recommended to protect the display system and to have better performance. power up sequence: start ? turn on the logic system in the application and power up the SSD1730 display off ? set column and row driver doff# to ?l? initialization ? send lp, yd, xscl and data stable ? wait for the power levels getting stable (around 80ms) # display on ? set column and row driver doff# to ?h? power down sequence: display off ? set column and row driver doff# to ?l? sleep mode ? set power chip to sleep mode by setting xslp to ?l? discharge ? wait for the discharge of the display system (around 50ms) # power down ? cut the power of the SSD1730 end ? turn off the logic system of the application # depends on the system loading. +v1
SSD1730 rev 2.0 04/2002 solomon 17 12. application circuit (SSD1730 5x step-up mode) vdd_row -v1 +v1 500k 510k 2sa 3.3m c17=470pf 2sj 2sk 2sk 2sk hc -v3b vem vdd_row -v1 vee xbb c7n ab c1p c1n c2p c2n c3p c3n c4p c4n v2 vss -v2 -v3 c5n c5p c6n c1nb c1pb c8n vdd=vdd_pwr vss lp xslp vdd vss l3 l2 l1 l0 xtst lp xslp xfr fr xfr v2 vc -v2 -v3 c1=4.7uf c2=4.7uf c3=4.7uf c4=4.7uf c5=4.7uf c6=4.7uf c7=4.7uf c10=4.7uf c11=0.1uf c8=1.0uf c9=1.0uf c18=1.0uf c14=0.1uf c13=1.0uf c15=1.0uf c16=1.0uf c19=1.0uf c12=4.7uf 3.3m fr v3 figure 12 - application circuit for SSD1730 5x step-up mode remark: hc is tied to ?v3b for 6x step-up mode.
solomon rev 2.0 04/2002 SSD1730 18 13. package dimensions 1 12 13 24 25 36 48 7.00 9.00 7.00 9.00 0.22 0.05 0.50 pin 1 identifier 1.6max 1.4 0.05 min0. 05 0.25 0.6 0.15 1.00 48 lqfp max 0.15 3.5 o 3.5 (dimension in mm, do not scale this drawing) figure 13 - package dimensions
SSD1730 rev 2.0 04/2002 solomon 19 solomon systech reserves the right to make changes without further notice to any products herein. solomon systech makes no warr anty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does solomon systech assume any liability a rising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or inciden tal damages. ?typical? parameters can and do vary in different applications. all operating parameters, including ?typicals? must be validated for each customer applicati on by customer?s technical experts. solomon systech does not convey any license under its patent rights nor the rights of others. solomon systech products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sust ain life, or for any other application in which the failure of the solomon systech product could create a situation where personal injury or death may occur. should buy er purchase or use solomon systech products for any such unintended or unauthorized application, buyer shall indemnify and hold solomon systech and its of fices, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising ou t of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that solomon systech w as negligent regarding the design or manufacture of the part.

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